1. Field of the Invention
The present invention relates generally to a method for manufacturing a semiconductor device, and more particularly to a method for forming a storage node contact of a semiconductor device, which can improve contact resistance while preventing misalignment between a landing plug poly and the storage node contact.
2. Description of the Prior Art
As an area available for forming a pattern decreases and a level difference increases due to high integration of semiconductor devices, it has become difficult to form a contact between a storage node and a substrate. Thus, in order to solve process difficulties caused by a high level difference, that is, in order to ensure a contact margin between a storage contact and a substrate, there has been universalized a technology in which a storage node contact is formed prior to the formation of the storage node.
Hereinafter, a conventional method for forming a storage node contact will be described in conjunction with FIGS. 1A to 1D.
Referring to FIG. 1A, a gate insulating film 13a, a gate conductive film 13b and a nitride film 13c as a hard mask are successively formed on a semiconductor substrate 11 on which a device separating film 12 has been formed, and then are patterned to form gates 13. Thereafter, spacers 14 are formed on both sidewalls of the respective gates 13 and then source/drain regions 15 are formed under substrate surfaces between the gates 13, including the spacers 14.
Next, after a first insulating interlayer 17 is deposited on the resultant substrate structure, a surface of the first insulating interlayer 17 is planarized and then the surface-planarized first insulating interlayer 17 is etched to form a landing plug contact which simultaneously exposes several gates 13 and substrate regions between the gates 13. Thereafter, a polysilicon film is deposited on the first insulating interlayer such that the landing plug contact is filled up. Then, the polysilicon film and the first insulating interlayer 17 are subjected to Chemical Mechanical Polishing (CMP) until the nitride film 13c as a hard mask is exposed to form a landing plug poly 18 on substrate regions between the gates 13.
Referring to FIG. 1B, a bit line (not shown) to be connected to a specific landing plug contact is formed on the entire surface of the substrate including the landing plug poly 18 and the gates 13. Here, the bit line is not shown in this figure because it is perpendicular to gate line. Thereafter, a second insulating interlayer 19 is deposited on the resultant substrate structure according to any well-known process such that the bit line is covered with the second insulating interlayer and then a surface of the second insulating interlayer is planarized.
Referring to FIG. 1C, the second insulating interlayer 19 is etched according to any well-known process to form a storage node contact hole H which exposes the landing plug poly 18.
Referring to FIG. 1D, the storage node contact hole H is filled up with a polysilicon film to form a storage node contact 20.
Such a conventional method for forming a storage node contact has a problem in that it is difficult to provide alignment between the landing plug contact and the storage node contact with decrease in contact area due to the high integration of semiconductor devices. Also, there is another problem of increase in resistance between the landing plug contact and the storage node contact.